Low level

concurrency

atomicity

atomic operations

ordering

barriers / fences

visibility

synchronizes-with happens-before

I. Atomicity

Uniprocessor system

Exchange and add

shared_ptr::~shared_ptr()
{
  if (count-- == 1)
  {
    deleted ptr;
  }
}

  xadd val,(ptr)

• Single instruction (since 486) - can't be interrupted
• lock prefix
  • always locks the bus for the duration of instruction
  • can be omitted for normal memory operations
  • required for example with DMA

Compare and exchange

void stack::push(const T& data) {
        node* new_node = new node(data);
 
        new_node->next = head;
        <context switch>
        head = new_node; 
}

bool __atomic_compare_exchange (type *ptr, type *pexp, type vnew);

void stack::push(const T& data) {
        node* new_node = new node(data);
 
        new_node->next = head;

        while(!__atomic_compare_exchange(
                &head,                     // ptr to value
                &new_node->next,           // ptr to expected value
                new_node)                  // new value
              ) ;
}

Compare and exchange - x86

  mov          (pexp), %eax    ; store expected in %eax
  cmpxchg      vnew, (ptr)     ; try store new in ptr
  sete         %cl             ;
  test         %cl,%cl         ; check cmpxchg status
  jne          _success        ; exit on sucess
  mov          %eax, (pexp)    ; move updated current value to expected
_success:

• Not a single instruction
• Requires loop to handle failures (interruptions)
• lock prefix not required for normal memory operations

II. Odering

Compile time

bool isReady = false;
Job* job = nullptr;

void prepareJob() {
  job = new Job();
  isReady = true;
}

void waitForJob() {
  while (!isReady) std::this_thread::yield();

  job->process();
}

compiled with -O0

0000000000400676 <_Z10prepareJobv>:
  sub    $0x8,%rsp
  mov    $0x1,%edi
  callq  400570 <_Znwm@plt>
  movb   $0x1,0x2009d5(%rip)        # 601060 <isReady>
  mov    %rax,0x2009c6(%rip)        # 601058 <job>
  add    $0x8,%rsp
  retq

compiled with -O2 (-fschedule-insns2)

0000000000400676 <_Z10prepareJobv>:
  sub    $0x8,%rsp
  mov    $0x1,%edi
  callq  400570 <_Znwm@plt>
  mov    %rax,0x2009cd(%rip)        # 601058 <job>
  movb   $0x1,0x2009ce(%rip)        # 601060 <isReady>
  add    $0x8,%rsp
  retq

COMPILE
time reordering

• Compiler assumes SINGLE-THREADED program:
  perfectly legal, user won't see the difference

// ...

void prepareJob() {
  job = new Job();
  asm volatile("" ::: "memory"); 
  isReady = true;
}

// ...

• Compiler barrier prevents compile time reordering
• Plain volatile keyword is not a compiler only barrier (prevents only volatile to volatile reoredering)

III. Atomicity

Cache coherent SMP system

Exchange and add

shared_ptr::~shared_ptr()
{
  if (count-- == 1)
  {
    deleted ptr;
  }
}

type __atomic_fetch_add (type *ptr, type val, int memorder)

shared_ptr::~shared_ptr() {
  if (__atomic_fetch_add(&count, -1, __ATOMIC_SEQ_CST) == 0) {
    deleted ptr;
  }
}

  lock xadd val,(ptr)

• lock prefix required - drains the store buffer
• cache lock instead of locking the bus - cache line is exclusive for the duration of the operation

  dmb     sy
_loop:
  ldrex   r0, [ptr]
  add     r0, val
  strex   r1, r0, [ptr]
  cmp     r1, #0
  bne.n   _loop
  dmb     sy
      

• ldrex - load the value and makes reservation (tags the address as exclusive)
• strex - stores the value if the address is still tagged as exclusive

• global monitor can tag one address for each processor
• the state of monitor is cleared when:
  • processor performs an exclusive load from a different location
  • different processor successfully performs a store at reserved location
  • during context switch

   sync
_loop:
   lwarx   r10,0,ptr
   add     r10,r10,val
   stwcx.  r10,0,ptr
   mcrf    cr7,cr0
   bne     cr7,_lop
   isync
      

Compare and exchange

void stack::push(const T& data) {
        node* new_node = new node(data);
 
        new_node->next = head;

        head = new_node; 
}

bool __atomic_compare_exchange_n (type *ptr, type *pexp, type vnew,
                                  bool weak, int success_memorder,
                                  int failure_memorder)

void stack::push(const T& data) {
        node* new_node = new node(data);
 
        new_node->next = head;

        while(!__atomic_compare_exchange_n(
                &head,                     // ptr to value
                &new_node->next,           // ptr to expected value
                new_node,                  // new value
                false,                     // weak vs strong
                __ATOMIC_SEQ_CST,          // success memory order
                __ATOMIC_SEQ_CST)          // failure memory order
              ) ;
}

Compare and exchange - x86

  mov          (pexp), %eax    ; store expected in %eax
  lock cmpxchg vnew, (ptr)     ; try store new in ptr
  sete         %cl             ;
  test         %cl,%cl         ; check cmpxchg status
  jne          _success        ; exit on sucess
  mov          %eax, (pexp)    ; move updated current value to expected
_success:

Compare and exchange - ARM

  ldr     vexp, [pexp, #0]   ; load the expected value
  dmb     sy                 ; memory barrier
_loop:
  ldrex   rval, [ptr]        ; load ptr to rval and make reservation
  cmp     rval, vexp         ; check if loaded value equals expected
  bne.n   _exit              ; exit otherwise
  strex   r0, vnew, [ptr]    ; try to store vnew to ptr
  cmp.w   r0, #0             ; check status
  bne.n   _loop              ; loop if lost reservation
_exit:
  dmb     sy                 ; memory barrier
  ite     ne                 ;
  movne   r1, #0             ; store the result
  moveq   r1, #1             ;
  cmp     r1, #0             ; check status
  bne.n   _success           ; exit on success
  str     rval, [pexp, #0]   ; move updated current value to expected
_success:

strong

weak

Compare and exchange - PowerPC

  sync                     ; memory barrier
_loop:
  lwarx   rval,0,ptr       ; load ptr to rval and make reservation
  cmpw    cr7,rval,vexp    ; check if loaded value equals expected
  bne     cr7, _exit       ; exit otherwise
  stwcx.  vnew,0,ptr       ; try to store vnew to ptr
  mcrf    cr7,cr0          ; get the result from conditional register
  bne     cr7, _loop       ; loop if lost reservation
_exit:
  isync                    ; memory barrier
  mfcr    r8               ; get the result from conditional register
  rlwinm  r8,r8,31,31,31   ;
  cmpwi   cr7,r8,0         ; check status
  bne     cr7, _success    ; exit on success
  stw     rval,0(pexp)     ; move updated current value to expected
_success:

IV. Ordering

Cache coherent SMP system

bool isReady = false;
Job* job = nullptr;

void prepareJob() {
  job = new Job();
  isReady = true;
}

void waitForJob() {
  while (!isRead) std::this_thread::yield();

  job->process();
}

STORES
reorder after
STORES

bool isReady = false;
Job* job = nullptr;

void prepareJob() {
  job = new Job();
  smp_wmb();
  isReady = true;
}

void waitForJob() {
  while (!isRead) std::this_thread::yield();

  job->process();
}

• Write memory barrier drains the store buffer
• It prevents runtime reordering of store operations

int done1 = 0, done2 = 0,  firstOne = -1;

int main(int argc, char* argv[]) {
    std::thread t1([&] {
        done1 = 1;
        if (done2) firstOne = 2;
    });

    std::thread t2([&] {
        done2 = 1;
        if (done1) firstOne = 1;
    });

    t1.join();
    t2.join();
    assert(firstOne == 1 || firstOne == 2);
}

STORES
reorder after
LOADS

bool isReady = false;
Job* job = nullptr;

void prepareJob() {
  job = new Job();
  smp_wmb();
  isReady = true;
}

void waitForJob() {
  while (!isRead) std::this_thread::yield();
  job->process();
}

LOADES
reorder after
LOADES

bool isReady = false;
Job* job = nullptr;

void prepareJob() {
  job = new Job();
  smp_wmb();
  isReady = true;
}

void waitForJob() {
  while (!isRead) std::this_thread::yield();
  smp_rmb();
  job->process();
}

• Read memory barrier drains the invalidate queue
• It prevents runtime reordering of load operations

Job* job = firstJob;
bool jobConsumed;

void consumer() {
  Job *oldJob = job;
  jobConsumed = 1;

  oldJob->process();
}

void producer() {
  if (jobConsumed) {
    job = nextJob;
  }
}

LOADES
reorder after
STORES

Source of reordering

• Optimizing compilers
• Cache coherent multi-core processing
• Multiple issue of instructions
• Out-of-order execution
• Speculation - branch predicting
• Speculative loads
• Load and store optimizations

Barrier types

• Each architecture has a different set of barriers
• High level functions mapped to platform specific instructions

Kernel barriers

• compiler barriers
  • barrier
• mandatory barriers - orders the whole system (visible all bus masters in system)
  • mb
  • rmb
  • wmb

• SMP barriers - ordering between cores/processors within an SMP system
  • smp_mb
  • smp_rmb
  • smp_wmb
• SMP half-barriers
  • smp_load_acquire
  • smp_store_release

Barrier instructions

Intel

• sfence - serializes all stores
• lfence - serializes all loads
• mfence - serializes all stores and loads
• locked instructions - serializes stores and loads
• each load is load-acquire and each store is store-release

ARM

• dmb st - serializes all stores
• dmb sy - serializes all stores and loads
• lda - load acquire - serializes all stores and loads that appear after the instruction (ARMv8)
• stl - store release - serializes all stores and stores that appear before the instruction (ARMv8)

POWERPC

• hwsync - orders stores and loads
• lwsync - allows store to pass load (used with st to achive store release)
• bc; isync - side effect used to achieve load acquire without hwsync

Memory model aware atomic

• atomic operations with memory order constrains
• since GCC-4.7, used by C++11 atomics
• constrains add barriers before/after atomic operations
• relaxed - no ordering
• acquire/release - acquire/release semantic
• sequential consistency - total order of operations

SEQ_CST

RELAXED

Memory model

• C++ - no support for multi threading till C++11
• C++11 - memory model aware atomics (full control)
• Java
  • java.util.concurrent.atomic guarantees atomicity and ordering
  • volatile guarantees ordering (every load/store have acquire/release semantic)

Visibility

Barrier parring

bool isReady = false;
Job* job = nullptr;

void prepareJob() {
  job = new Job();
  smp_wmb();
  isReady = true;
}

void waitForJob() {
  while (!isRead) std::this_thread::yield();
  smp_rmb();
  job->process();
}

• Barriers may have no effect if both communicating thread do not use them
• write barrier pairs with load barrier
• acquire barrier pairs with release barrier
• general barrier pairs with other barriers

synchronizes-with / happens-before

std::atomic<int> isReady(0);
Job* job = nullptr;

void prepareJob() {
                      | Job* tmp = (Job*) malloc(sizeof(Job));
                      | tmp->field1 = 1;
  job = new Job();  <-| tmp->field2 = 2;
                      | job = tmp;

  isReady.store(1, std::memory_order_release);

  // do some other stuff
}

void waitForJob() {
  while (!  isReady.load(std::memory_order_acquire)) {};
  job->process();
}

• store release synchronizes with load acquire ...
• ... so construction of Job (all the stores and loads) happens before process method
• ... assuming the load has returned 1

• think of it as batching system
  • memory barrier divides operation into batches
  • synchronises-with make a new batch visible (we are publisihing the state)

#1

#2

• when the values becomes visible?
  • can't say when
• to whom it becomes visible?
  • single-copy atomic - to all cores at the same time (Intel, ARM with lda/stl)
  • multiple-copy atomic - to each core at different time (ARM, PowerPC)

Why do I need this?

• all synchronization primitives are build using atomics and barriers
• to understand C++/Java/.Net memory model
• crucial when creating lock-free code
• to avoid common mistakes
  • broken double check locking
  • broken Dekker's algorithm

Thank you